1. Field of the Invention
The present invention relates to a semiconductor device having circuits structured with thin film transistors (hereinafter referred to as TFT). For example, the present invention relates to the structure of electro-optical devices, typically liquid crystal display panels, and the structure of electronic equipment loaded with the electro-optical devices as parts. Note that throughout this specification semiconductor device indicates general devices that acquire their functions through the use of semiconductor characteristics, and that electro-optical devices, semiconductor circuits, and electronic equipment are also semiconductor devices.
2. Description of the Related Art
A TFT can be formed on a transparent glass substrate, so that the development of applications to active matrix type liquid crystal display devices has been positively carried out. High mobility can be obtained in a TFT utilizing a crystalline semiconductor film (hereinafter referred to as crystalline TFT), so that functional circuits are integrated on the same substrate to realize high definition image displays.
When active matrix type liquid crystal display devices have a highly minute screen resolution, it follows that one million TFTs are necessary number of pixels alone. Further, by adding a functional circuit, an even higher number of TFTs becomes necessary. In order to operate a liquid crystal display device stably, it is necessary to ensure the reliability of each individual TFT, and to operate them stably.
However, TFTs are not always equal from a reliability standpoint to MOS transistors manufactured on a single crystal semiconductor substrate. The off current (leak current) is liable to become large for a TFT, so that the phenomenon of a drop in mobility and in the on current has frequently been observed, if operated over a long period of time. As one cause for the occurrence of these phenomenons, it is thought that there is a degradation of the properties due to a hot carrier generated by an increase in the channel electric field.
On the other hand, the LDD (lightly doped drain) structure is well known as a technique for increasing the reliability with a MOS transistor. This structure has, on the inside of the source and drain regions, an even lower concentration impurity region. This low concentration impurity region is called an LDD region, and this structure can be employed with a TFT. With conventional techniques, the low concentration impurity region that becomes the LDD region is formed by a first impurity doping process using a gate electrode as a mask, and thereafter an anisotropic etching technique is utilized to form sidewalls on both sides of the gate electrode. High concentration impurity regions that become the source and drain regions are formed by a second impurity doping process using the gate electrode and the sidewalls as masks.
In addition, a structure in which the LDD region overlaps the gate electrode to some degree, through a gate insulating film, is known for a MOS transistor. There are several methods for forming this structure, and for example, GOLD (gate-drain overlapped LDD) and LATID (Large-tilt-angle implanted drain) are known. By using this type of structure, it is possible to lower the impurity concentration in the LDD region, and the hot carrier tolerance can be increased as the effective relaxation on the electric field becomes larger.
In addition, attempts have been made in which these MOSFET advantages are applied to a TFT. For example, Hatano et al (M. Hatano, H. Akimoto, and T. Sakai, IEDM97 Technical Digest, p. 523-6) realized a GOLD structure that uses sidewalls formed by silicon.
However, compared with a normal LDD structure, the structure published in the paper has a problem in that the off current (the current that flows when the TFT is in the off state) gets large, and hence a countermeasure therefor is necessary.
In order to attain high reliability with a TFT, it is necessary to examine from an element structure perspective, as in the MOS transistor technical field. However, an LDD region can be formed in a self-aligning manner, with the conventional method stated above, but it is difficult to have the gate insulating film remain well in selectiveness with the anisotropic etching process for the sidewall film, and this leads to property variations. Also, there remains a problem in that an off current is large.